The present invention relates generally to the field of microelectronics and more particularly to a method and structure for optical and electrical isolation between adjacent integrated devices.
Optical and electrical isolation between active devices is often an important requirement for integrated micro-systems, especially those involving optical sensors. A number of solutions to electrically isolate adjacent devices are available, including local oxidation of silicon (LOCOS), shallow trench isolation (STI) and deep trench isolation (DTI). When properly designed, these isolation structures can reduce unwanted diffusion of dopants, prevent and/or reduce capacitance coupling, or prevent latch-up between adjacent devices. However, these solutions do not provide any optical isolation between adjacent devices. In addition, a LOCOS structure usually leaves a wafer with a non-planar top surface, which can cause difficulties for subsequent fabrication processes. Depending on the trench depths, traditional trench isolation methods often require a significant amount of trench-filling material to be deposited, which often necessitates additional effort in the planarization step(s).
These and other drawbacks exist in known systems and techniques.